Curriculum Vitae
Utkarsh Kumar Ph.D. Candidate, Electrical and Computer Engineering Kumar.ut@northeastern.edu | LinkedIn | ut1991.github.io | (617) 671-4753 | Boston, MA
Ph.D. Candidate in Electrical and Computer Engineering specializing in low-power Analog, RF, Mixed-Signal, and Photonics IC design. Experienced in PMICs, RF front ends, PLLs, data converters, RF filters, and energy-efficient wireless systems. Skilled in circuit and PCB design, schematic and layout implementation, SI/PI analysis, EM simulation, silicon validation, and RF hardware characterization. Seeking full-time roles in analog, RF, mixed-signal, and PMIC design, contributing across the IC development cycle from architecture and circuit design to silicon validation.
Education
- Ph.D. in Electrical and Computer Engineering — CGPA: 3.85/4.00
Northeastern University, Boston, MA, USA Jan 2023 – Present - Research Specialization: Low-power Analog, RF, Mixed-Signal, and Photonics IC Design
- Relevant Coursework: Power Management ICs, Analog IC Design, RF IC Design, Solid State Devices
- M.Tech. in Electronics & Communication Engineering — CGPA: 9.20/10, Gold Medalist
Pondicherry Central University, Pondicherry, India Aug 2014 – June 2016 - Relevant Coursework: Low-Power VLSI, MEMS, Advanced Radiation Systems
- B.Tech. in Electronics & Communication Engineering — CGPA: 8.80/10, Distinction
Hindustan University, Chennai, India Aug 2009 – May 2013 - Relevant Coursework: Analog Circuits I & II, Electronic Devices, Digital Circuits, Wireless Communications
Core Technical Expertise & Circuit Blocks
- Primary IC Design Domains: Advanced hardware security primitives, high-efficiency RF energy harvesting microsystems, and energy-detection based RF architectures optimized for ultra-low power operation and enhanced physical-layer security of IoT and biomedical devices.
- RF & Microwave Front-End Architectures: Low-Noise Amplifiers (LNAs), Power Amplifiers (PAs), Active/Passive Mixers, Gilbert Cell Multipliers, Voltage-Controlled Oscillators (VCOs), Ring Oscillators, LC Tank Cavities, Injection-Locked Oscillators, Phase Shifters, Attenuators, High-Frequency RF Filters (BAW/SAW), RF Front-End Modules (FEM), and Wideband Impedance Matching Networks.
- Analog Core Blocks & Circuits: High-Gain Op-Amps with advanced frequency compensation networks, Operational Transconductance Amplifiers (OTAs), Instrumentation Amplifiers, Differential Pairs, Active/Passive Filters, Programmable/Variable Gain Amplifiers (PGAs/VGAs), Precision Current Mirrors, and Stable Voltage References.
- Mixed-Signal & Data Conversion Blocks: High-Speed Latching Comparators, Dynamic Latches, Sample-and-Hold (S/H) and Track-and-Hold (T/H) circuits, ADCs (SAR, Sigma-Delta, Pipelined, Flash), and DACs (Current-Steering, R-2R).
- Clock Generation & PLL Systems: Phase-Locked Loops (PLLs), Charge Pumps, Phase-Frequency Detectors (PFD), Frequency Dividers/Prescalers, Loop Filters, Clock and Data Recovery (CDR) architectures, and High-Speed Clock Distribution Networks.
- Power Management IC (PMIC) Blocks: Low-Dropout Regulators (LDOs), Bandgap References (BGR) with startup mechanics, Charge Pumps, Buck/Boost Switching Power Converters, Voltage Clamps, and Rectifiers.
- High-Speed Serial Links & Signaling: SerDes architectures, Equalizers (CTLE, DFE, FFE), High-Speed Transmitter Drivers, Optical Modulator Drivers, Transimpedance Amplifiers (TIAs), and Integrated Optical/Photonics Interconnects.
- Simulation, Verification & Silicon Validation: Translating transistor-level schematics into verified physical layouts; pre-/post-layout parasitic extraction (RCX/PEX) validation, rigorous PVT corner analysis, and statistical mismatch characterization for yield optimization and debugging.
Skills
- Programming & Scripting: Verilog, Verilog-A, System Verilog, VHDL, C, Python (NumPy, SciPy, Matplotlib), Shell scripting, Perl, TCL
- IC Design & Tools: Cadence Virtuoso, Spectre, ORCAD PSpice, Keysight ADS, Ansys HFSS, COMSOL Multiphysics, Synopsys RTL2GDS Digital Flow, MATLAB, Simulink, TCAD
- Analog & RF Subsystems: BAW/SAW Filter design, LNA, PA, PLL, Mixers, BGR, OTAs, LDOs, Rectifiers, Matching Networks, Oscillators
- Documentation & Data Tools: Microsoft Excel (data analysis, charting), Word (technical documentation), PowerPoint (presentations), LaTeX
- RF Lab Instrumentation: Vector Network Analyzers (VNAs), Digital Storage Oscilloscopes, Spectrum Analyzers, DC Power Supplies, High-Frequency Function/Signal Generators, Digital Multimeters (DMMs), Logic Analyzers
Sponsored Research Projects (DARPA/NSF Grant)
Energy-Detection RF Architectures for Secure IoT June 2025 – Present - Designing energy detection-based RF circuits tailored for ultra-low power operation and enhanced hardware security of next-generation IoT devices.
Energy-Efficient PLL-Based Frequency Synthesizer October 2024 – June 2025 - Developed energy-efficient PLL-based frequency synthesizers optimized for distributed beamforming networks and next-generation wireless communications systems.
Protecting Analog and Mixed-Signal Circuits Using Switch-Mode Time-Domain Locking May 2023 – March 2024 - Researched and developed advanced methodologies for safeguarding sensitive analog and mixed-signal ICs using custom switch-mode time-domain locking state frameworks to prevent reverse engineering and unauthorized hardware tampering.
Sub-microwatt RF Energy Harvesting Integrated Circuit January 2023 – November 2023 - Built ultra-low power sub-microwatt RF energy harvesting ICs featuring high-efficiency rectifiers and intelligent power management architectures for battery-free IoT nodes and biomedical implant applications.
Silicon Design & Academic Projects
- 45nm CMOS Bandgap Reference (BGR): Modeled and designed a precision 45nm CMOS bandgap reference circuit achieving a highly stable temperature drift profile of less than 1 mV/°C across critical thermal swings for high-accuracy on-chip biasing networks.
- 65nm CMOS Low-Dropout (LDO) Regulator: Implemented a 65nm CMOS LDO regulator achieving 100 mV load regulation and a rapid sub-5 microsecond transient recovery response across a variable 1–50 mA load envelope.
- 9-bit Differential SAR ADC: Fabricated and designed a 9-bit differential charge-redistribution SAR ADC in TSMC 65nm technology, achieving 50.5 dB SNDR and 59.5 dB SFDR at an ultra-low power consumption of 233 µW under a 1 V supply.
- Logarithmic RSSI Transceiver Chain: Configured a high-dynamic-range RSSI current-summing architecture coupled with multi-stage limiting amplifiers for integrated spectrum sensor blocks and energy detection infrastructure.
Professional Experience
RF Filter Design Co-Op | Skyworks Solutions Inc.
California, USA | July 2024 – December 2024
- Spearheaded the architectural design, EM modeling, and physical validation of BAW and SAW filters tailored for next-generation RF front-end modules operating across the 4–10 GHz regime.
- Achieved state-of-the-art return loss optimization (S11 < −35 dB) alongside an insertion loss profile of < 2 dB across active bands.
- Developed integrated matching networks and LNA–filter co-design topologies, implementing strict wideband linearity constraints and achieving > 30 dB out-of-band isolation.
- Managed complete schematic engineering, multi-layer EM modeling, and post-layout parasitic extraction in Keysight ADS, Cadence Virtuoso, and Ansys HFSS, correlating simulation models with on-chip silicon bench testing.
RF & Signaling Operations Engineer | Indian Railways
Chennai, India | February 2018 – January 2023
- Monitored and optimized mission-critical, high-reliability RF signaling distribution networks, telemetry data links, and complex electromechanical interlocking platforms.
- Managed the deployment, testing, and field maintenance of long-range wireless RF links, multi-channel hardware data loggers, analog sensor loops, and track-level sub-systems.
- Performed field-level technical commissioning, strict safety audits, real-time rapid troubleshooting, and preventive maintenance scheduling on critical signaling components.
Teaching Experience
Teaching Assistant – Fundamentals of Electronics (EECE 2413) Northeastern University - Assisted students with core analog and digital electronics concepts, including diodes, BJTs, MOSFETs, and basic amplifier circuits.
- Conducted lab sessions covering circuit construction, measurement techniques, and use of oscilloscopes, function generators, and multimeters.
- Graded assignments, exams, and lab reports; held office hours to reinforce fundamental circuit analysis and design concepts.
Teaching Assistant – Power Management Integrated Circuits (EECE 7250) Northeastern University Jan 2025 – Apr 2025 - Assisted in the design and analysis of analog/RF power circuits, including LDOs, BGRs, charge pumps, and power converters.
- Guided students in Cadence Virtuoso schematic design, simulation, and layout of CMOS analog circuits.
- Taught key PMIC concepts including startup, dropout, PSRR, stability, and transient response; evaluated laboratory assignments.
Teaching Assistant – Circuits and Signals for Biomedical Applications (EECE 2150) Northeastern University Jan 2024 – Apr 2024 - Guided students in analog CMOS circuit design and simulation using Cadence Virtuoso, MATLAB, and SPICE.
- Taught key analog building blocks, including op-amps, current mirrors, differential pairs, and active filters.
- Supervised layout implementation and performance evaluation through frequency, transient, and compensation analysis.
Publications
- Protecting Analog Circuits Using Switch-Mode Time-Domain Locking — IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, IEEE Xplore
- Non-Iterative Square Wave Modeling of Multistage CMOS Dickson Rectifiers for RF Energy Harvesting — IEEE Open Journal of Circuits and Systems (OJCAS)
- A 69.3% Efficient, −25 dBm Sensitivity, 29 dB PDR Leakage-Clamped Gate Rectifier for Beamforming and Neural Implants — IEEE Transactions on Circuits and Systems I (TCAS-I) (Submitted)
- Adaptive Dual-Path CMOS Rectifier for RF Energy Harvesting with −37 dBm Sensitivity and 35 dB Power Dynamic Range — IEEE MWSCAS
- Surrogate-Assisted Operating-Point Selection for RF Energy Harvesting Rectifiers — IEEE MWSCAS
- Design of CPW-fed E with Inverted L-shaped Antenna for Multiband Wireless Application — IEEE International Conference on Communication and Computational Intelligence (ICCCI), IEEE Xplore
- A Switch-Mode Time-Domain Locking SC Voltage Converter with HCI-Based Key-Selective Self-Destruction — Journal of Cryptographic Engineering (JCEN), Springer Nature (Submitted)
Talks & Presentations
MWSCAS 2026 — IEEE International Midwest Symposium on Circuits and Systems, Cincinnati, OH August 2026 NEHWS 2026 — New England Hardware Security Day, Tufts University, Medford, MA April 24, 2026 IEEE ICIIECS 2016 — 3rd International Conference on Innovations in Information, Embedded and Communication Systems, Karpagam College of Engineering, Coimbatore, India March 2016 IEEE ICECS 2016 — 3rd International Conference on Electronics and Communication Systems, Karpagam College of Engineering, Coimbatore, India February 2016 IEEE ICCCI 2016 — International Conference on Computer Communication and Informatics, Sri Shakthi Institute of Engineering and Technology, Coimbatore, India January 2016 ICMARS 2015 — 11th International Conference on Microwaves, Antenna, Propagation & Remote Sensing, Jodhpur, India December 2015